Nonvolatile flash memories (e.g., NAND-type flash EEPROMs), are used in various applications, such as portable computers (or notebook computers), hand-held sets (e.g., cellular phones), and palm top computers. Flash memories are important components also in the field of media technology, for instance in answering machines recording voice with audio information, and digital still cameras producing video information.
As flash memories are adaptable to their own interfacing forms different from those of other kinds of memories such as DRAMs and SRAMs, it is necessary to adapt them for use in such systems. In the flash memories, address signals and input/output data signals are transferred through a plurality of pins. And the flash memories should receive command signals that distinguish signals into addresses, data, or commands.
A general flash memory shown in FIG. 1 has row address buffer 10, row decoder 20, column address buffer 30, column decoder 40, memory cell array 50, page buffer 60, column gate circuit 70, and data output buffer 80. Row address buffer 10 and row decoder 20 receive and store external row address XRA, and apply the latched row address to memory cell array 50 after decoding it. Column address buffer 30 and column decoder 40 receive and store external column address XCA, and apply the latched column address to column gate circuit 70 after decoding it. Memory cell array 50 is formed of a plurality of memory cells constructing a plurality of strings (e.g., NAND string in a NAND-type flash memory), in which a plurality of word lines and bit lines are arranged in a matrix form. The memory cells are arranged at intersections of rows and columns. Page buffer 60 detects and stores data signals read from the memory cells, or data signals to be stored in the memory cells identified be the addresses. Column gate circuit 70, also known as Y-Gate circuit, transfers the data held in page buffer 60 to data output buffer 80 in response to the column address. Data output buffer 80 outputs the data supplied from page buffer 70 through input/output pins.
An operation of the device of FIG. 1, is shown in FIG. 2. The suffix "B" of a signal name denotes the signal activates in negative logic for example, CEB stands for "CE-bar". As control signals CEB, WEB and CLE go to their activation levels, a command signal, e.g., 00h, informing a read mode is invited via input/output pins I/O (not shown) thereto. Next, when control signal ALE goes to high level, the row and column address are applied thereto through input/output pins in synchronization with control signal WEB.
After completing the receiving operation with the read command signal and addresses, control signal R/BB falls to low level from high level, so as to put the device into a busy state, in which data of memory cells are read out and stored in the page buffer 60. When signal R/BB goes to high level from the low level, the device is placed into a ready state, and the detected data is applied to the outside of the device. It can be seen that the flash device does not perform its read-out operation until the command signal and addresses are invited thereto.
In adapting the flash memory device for use with a boot-up memory component, there is a problem. For example, for a personal computer, a boot-up memory should have a primary function of supplying pre-programmed boost-up data (i.e., firmware) relevant to an established system information or BIOS configurations therein, when the system is powered up. Since a central processor unit of a computer system does not actually operate before a predetermined firmware with the boost-up memory, prior art systems are generally designed to be automatically initiated by the boot-up memory. This permits the boot-up memory to have a simple interfacing configuration. However, the flash memory of FIG. 1 demands the corresponding control signals (or strobe signals) before the input of the command and address signals. As such, the flash memory at FIG. 1 is not compatible with the boot-up procedure of prior art devices, even though it would have functional advantages as the boot-up storage component in a computing system.